SMTC Semiconductor Manufacturing and Testing Center

SMTC

SVNIT, SURAT

Abhishek Acharya and Aand Bulusu, "Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: a Physical Insight", ISCAS 2023, California, USA, May 21 - 25, 2023.
S. Srivastava, S. Panwar, M. Shashidhara, D. Joshi, N. Bagga and Abhishek Acharya, "Performance Investigation of Source/Drain Extension Region on Nanosheet FET: A Digital Design Perspective", Jun. 2023, Kyoto, Japan.
S. Panwar, S. Srivastava, M. Shashidhara, D. Joshi, P. Dubey and Abhishek Acharya, "Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs", Jun. 2023, Kyoto, Japan.
V. P. Bhale, D. R. Rotake, and A. D. Darji, "Analysis of PDMS polymeric material for heavy metal ions sensing application," in 2023 IEEE International Symposium on Smart Electronic Systems (iSES), pp. 93-98, 2023.
Optimization of BiOI/HTL Heterojunction for Efficient Charge Extraction from Solar Cell: For Indoor Light Harvesting, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
Prospective Performance Enhancement of Cu2BaSn(S,Se)4 Based Solar Cell by Optimizing Buffer Layer and Metal Contact, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
Numerical Simulation: Design and Optimization of CsSnI3 and Cs3Sb2Br9 based Multijunction Solar Cell, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
Investigation of ETL/Absorber heterojunction for Efficient Charge Extraction from Formamidinium Tin-based Perovskite Solar Cell, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
Numerical Investigation of Lead-Free Halide Perovskite with All-Inorganic Transport Layer, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
InGaAs-based MQWs Photovoltaic under Concentrated Light, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
Effect of ETL, and MAPbBrI3 Quantum Dots at HTL/absorber interface on the performance of (Sn,Ge) based perovskite solar cells, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
Investigation of ETL/Absorber Heterojunction for Efficient Charge Extraction from Formamidinium Tin-Based Perovskite Solar Cell, "40th European Photovoltaic Solar Energy Conference (EUPVSEC)", Lisbon, Portugal, September 18-23, 2023
Unveiling the potential of CuPbSbS3 for Photovoltaic application,” 20th International Workshop on The Physics of Semiconductor Devices (IWPSD), IIT Madras, India, December 17-20, 2023.
Evaluating the performance of Lead-free double Perovskite Cs2AgBiBr6 based solar cell” 20th International Workshop on The Physics of Semiconductor Devices (IWPSD), IIT Madras, India, December 17-20, 2023.
S. Srivastava, S. Panwar, M. Shashidhara , S. Yadav and Abhishek Acharya, "9th International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Tarragona, Spain, 2023.
C. Yeswanth, S. Panwar, S. Srivastava, D. Joshi, S. M and A. Acharya, "Configurable 8T SRAM-based Computing In- Memory Architecture for Enabling Shift Operation and Multibit Dot-Product Engines," DevIC 2023, Kalyani, India, pp. 330-334.
A. K. Gupta and A. Acharya et al., "9T SRAM Cell for Computation-In-Memory Architectures: Proposal & Investigation," DevIC 2023, Kalyani, India, pp. 282-286.
S. Panwar, M. Shashidhara , S. Srivastava, D. Joshi and Abhishek Acharya, "Performance Optimization of Epitaxial-Layer Based Si/SiGe Hetero-junction Area Scaled Tunnel FET Label-Free Biosensors Considering Steric Hindrance", EUROSOI-ULIS 2023, Tarragona, Spain.
S. S. Nayak, A. D. Darji, and P. K. Shah, "Automatic detection of COVID-19 from speech signal using machine learning approach," in 2023 IEEE 11th Region 10 Humanitarian Technology Conference (R10-HTC), pp. 19-23, 2023.
A. Gupta, P. Dakhare, R. Bhagat, D. Rotake, and A. D. Darji, "Fabrication of printed circuit board interdigitated electrode sensor for cadmium detection," in 2023 IEEE 8th International Conference for Convergence in Technology (I2CT), pp. 1-6, 2023.
S. B. Vishwajeet, V. Solanki, and A. D. Darji, "Design of hardware efficient approximate DCT architecture," in 2023 36th International Conference on VLSI Design and 2023 22nd ..., 2023.
M. Shashidhara , S. Srivastava, S. Panwar, and Abhishek Acharya, "Spin-Orbit Torque Magnetic Tunnel Junction based on 2-D Materials: Impact of Bias-Layer on Device Performance", EUROSOI-ULIS 2023, Tarragona, Spain.
Deepak Joshi, Satyabrata Dash, S. Reddy, et al., “Multi-objective Hybrid Particle Swarm Optimization and its Application to Analog and RF Circuit Optimization”, Circuits Systems Signal Process, 2023. DOI: 10.1007/s00034-023-02342-1.
Shail Pandey, Akash Agarwal, and Deepak Joshi, “Rotating magnetic field configuration for controlled particle flux in material processing applications”, International Journal of Materials Research, 2023. DOI: 10.1515/ijmr-2021-8756.
Yadav, S., Joshi, D., Kalita, S., Singh, T., “Quantum Tunnelling and Themonic Emission, Transistor Simulation”, In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. DOI: 10.1007/978-3-031-21514-8_11.
A. P. Shah, S. Dasgupta, A. Darji, and J. Tudu, "VLSI Design and Test: 26th International Symposium, VDAT 2022, Jammu, India, July 17–19, 2022, Revised Selected Papers," Springer Nature, 2022.
K. C. Pathak, A. D. Darji, and J. N. Sarvaiya, "Novel Low-Complex 4× 4 and 16× 16 Intra-prediction Architecture for Error Concealment for H. 264," in Proceedings of the Fourth International Conference on Microelectronics and Telecommunication Engineering (ICME), 2021.
I. Z. Mitrovic, P. Das, L. A. H. Jones, J. T. Gibbon, V. R. Dhanak, R. Mahapatra, T. P. Manzanera, J. W. Roberts, R. Potter, P. R. Chalker, S.-J. Cho, I. G. Thayne, “(Invited) Band Line-up of High-k Oxides on GaN”, ECS Transactions, v. 97, 2021. DOI: 10.1149/09701.0067ecst.
Yeswanth Chakka and Abhishek Acharya, "In memory Computing based Boolen and logical Circuit Design using 8T SRAM", May, 2021.
Manisha Mogili and Abhishek Acharya, "Design and Analysis of III-V Tunnel FET based Energy Efficient Digital Circuits", May, 2021.
Aman K. Gupta and Abhishek Acharya, "Exploration of 9T SRAM Cell for In Memory Computing Application", May, 2021.
Atul K. Yadav and Abhishek Acharya, "Investigation of III-V Tunnel FETs for Analog Circuit Design", May, 2021.
S. B. Tekin, P. Das, A. D. Weerakkody, N. Sedghi, S. Hall, I. Z. Mitrovic, M. Werner, J. S. Wrench, P. R. Chalker, “Single and Triple Insulator Tunnel Rectifiers for Infrared Energy Harvesting”, EUROSOI-ULIS 2020, Normandy, France (Virtual). DOI: 10.1109/EUROSOI-ULIS49407.2020.9365388.
K. Desai, A. D. Darji, and H. M. Singapuri, "Implementation of High speed, Low Power Modified Vedic Multiplier and Its Application in Lifting based Discrete Wavelet Transform," in TENCON 2019-2019 IEEE Region 10 Conference (TENCON), pp. 2387-2391, Oct. 2019.
L. A. H. Jones, P. Das, T. P. Manzanera, J. T. Gibbon, R. Potter, P. R. Chalker, R. Mahapatra, V. R. Dhanak, I. Z. Mitrovic, “Atomic Layer Deposited TiO2/Al2O3 Nanolaminates on GaN”, Insulating Films on Semiconductors (INFOS) 2019, Clare College, University of Cambridge, UK. (Talk given by P. Das)
P. Das, S. N. Supardan, J. W. Roberts, V. R. Dhanak, I. Z. Mitrovic, R. Mahapatra, “Band alignment of ALD deposited ZrO2/GaN for MIS-HEMT applications”, International Workshop on Physics of Semiconductor Devices (IWPSD) 2019, IIT Delhi, Delhi, India. (Talk given by R. Mahapatra)
N. Chatterji, A. Antony, and P. R. Nair, "Interface quality: Effect on performance of Silicon based Carrier Selective solar cells," in ICONMAT 2019, 2019.
Abhishek Acharya and Bulusu Anand, “Influence of Body-Bias and Gate-Source Overlap Length on the Analog Performance of Epitaxial Layer Enabled Area Scaled Tunneling FETs”, Jan. 2019, New Delhi, India.
Satyabrata Dash, Deepak Joshi, Ayushparth Sharma, Gaurav Trivedi, “A hierarchy in mutation of genetic algorithm and its application to multi-objective analog/RF circuit optimization”, Analog Integrated Circuits and Signal Processing, 2018. DOI: 10.1007/s10470-017-1090-4.
Satyabrata Dash, Sukanta Dey, Deepak Joshi, Gaurav Trivedi, “Minimizing area of VLSI power distribution networks using river formation dynamics”, Journal of Systems and Information Technology, 2018. DOI: 10.1108/JSIT-10-2017-0097.
Satyabrata Dash, Deepak Joshi, Gaurav Trivedi, “Multiobjective analog/RF circuit sizing using an improved brain storm optimization algorithm”, Memetic Computing, 2018. DOI: 10.1007/s12293-018-0262-9.
Anil Kumar, Shaurya Arya, N. Chatterji, A. Antony, and P. R. Nair, "Rear Contact Dependent Performance Enhancement of PEDOT:PSS/n-Si Solar Cell," in 4th IEEE ICEE 2018, 2018.
N. Chatterji, A. Antony, and P. R. Nair, "Effect of bulk doping in Si based carrier selective solar cells," in 4th IEEE ICEE, 2018.
Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “Understanding Drain Current Saturation and VDSAT Extraction in Tunnel FETs: Analog Design Outlook”, Jan. 2018, Pune, India.
Shivendra Yadav, Dheeraj Sharma, Mohd. Aslam, and Deepak Soni, “A Novel Analysis to Reduce Leakage Current in Charge Plasma Based TFET", INDICON, pp. 1-3, ISSN: (2325-9418), IIT Roorkee, Uttarakhand India, Dec. 2017, DOI: 10.1109/INDICON.2017.8487606.
Deepak Soni, Dheeraj Sharma, Shivendra Yadav, Mohd. Aslam, and Dharmendra Singh Yadav, “Gate Metal Workfunction Engineering for the Improvement of Electrostatic Behaviour of Doped Tunnel Field Effect Transistor", IEEE International Symposium on Nano Electronics and Information Systems (IEEE INIS 2017), pp. 190-194, OIST Bhopal, Dec. 2017, India, DOI: 10.1109/iNIS.2017.47.
Deepak Joshi, Satyabrata Dash, H. S. Jatana, Ratnajit Bhattacharjee, Gaurav Trivedi, “Analog circuit optimization using adjoint network based sensitivity analysis”, AEU - International Journal of Electronics and Communications, 2017. DOI: 10.1016/j.aeue.2017.08.053.
Deepak Joshi, Satyabrata Dash, Ayush Malhotra, Pulimi Venkata Sai, Rahul Das, Dikshit Sharma, Gaurav Trivedi, “Optimization of 2.4 GHz CMOS Low Noise Amplifier Using Hybrid Particle Swarm Optimization with Lévy Flight”, Proceedings - 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017. DOI: 10.1109/VLSID.2017.9.
N. Chatterji, "Modeling of interface dependent efficiency and temperature coefficient of silicon based carrier selective solar cells," in Mumbai, 2017.
Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “Impact of Device Design Parameters on VDSAT and Analog Performance of TFETs”, Jun. 2017, Kyoto, Japan.
K. Sawangsri, P. Das, S. N. Supardan, I. Z. Mitrovic, S. Hall, R. Mahapatra, A. K. Chakraborty, R. Treharne, V. R. Dhanak, K. Durose, P. R. Chalker, “Experimental band alignment of Ta2O5/GaN for MIS-HEMT applications”, Insulating Films on Semiconductors (INFOS) 2017, Potsdam, Germany. (Talk given by I. Z. Mitrovic)
P. Das, S. N. Supardan, I. Z. Mitrovic, V. R. Dhanak, A. Shaw, S. Hall, A. K. Chakraborty, R. Mahapatra, “Band Alignment of Sputtered Al2O3/GaN for MIS-HEMT Applications”, International Workshop on Physics of Semiconductor Devices (IWPSD) 2017, Kolkata, India. (Poster presented by P. Das)
Satyabrata Dash, Deepak Joshi, Gaurav Trivedi, “CMOS analog circuit optimization via river formation dynamics”, 26th International Conference Radioelektronika, RADIOELEKTRONIKA 2016. DOI: 10.1109/RADIOELEK.2016.7477393.
Deepak Joshi, Satyabrata Dash, Ujjawal Agarwal, Ratnajit Bhattacharjee, Gaurav Trivedi, “Analog circuit optimization based on hybrid particle swarm optimization”, Proceedings - 2015 International Conference on Computational Science and Computational Intelligence, CSCI 2015. DOI: 10.1109/CSCI.2015.112.
Deepak Joshi, Satyabrata Dash, Ratnajit Bhattacharjee, Gaurav Trivedi, “A method of analog circuit optimization using adjoint sensitivity analysis”, Proceedings of 25th International Conference Radioelektronika, RADIOELEKTRONIKA 2015. DOI: 10.1109/RADIOELEK.2015.7129048.
N. Chatterji, S. Khatavkar, C. Voz, A. Morales-Vilches, J. Puigdollers, and P. R. Nair, "A critical analysis on the role of back surface passivation for a-Si/c-Si heterojunction solar cells," in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), pp. 2456-2458, 2014.

Conference Proceedings