Currrent Students

  • Ph. D.

    Mitul Nagar

    Low power processor architecture for IoT Applications.

  • Ph. D.

    Swati

    Hardware Architecture for Embedded CNN

  • Ph. D.

    Smita Daware

    Hardware Architecture for MIMO

  • Ph. D.

    Aditya Prajapati

    Software Defined Networking

  • Ph. D.

    Rinkesh Patel

    Drone Technology

  • M. Tech.

    Harsh Parmar

  • M. Tech.

    Sudhanshu Kumar Yadav

Past Students

  • M. Tech.

    Sayantan Maiti

    Performance Optimization of Multi Core RISC-V Architecture for Face Recognition Algorithm

  • M. Tech.

    RANAJOY SADHUKHAN

    FPGA based Accelerator design for Variable dimension Convolution for CNN

  • M. Tech.

    Rohit Verma

    Hardware Based Packet Classification Algorithms

  • M. Tech.

    Rahul Kumar

    Performance Assessment of RISC-V Based Multiprocessor System

  • M. Tech.

    Dheeraj Verma

    Evaluate Convolution Layer and Optimize by Quantization Technique on Hardware

  • M. Tech.

    Suraj Gajbhiye

    Architecture evaluation of Various Processors for Vehicle License Plate Detection

  • M. Tech.

    Vignesh D

    Modular CNN based Object Tracking Implementation in FPGA Systems

  • M. Tech.

    Aryan Gamit

    Improving 3D Face Quality using Generative Adversarial Network

  • M. Tech.

    Gyaneshwar Rathore

    Design of MAC unit for RISC-V based IoT node

  • M. Tech.

    Krupa Chaudhari

    HDL Implementation of License Plate Extraction algorithm

  • M. Tech.

    Gangadhar Pasupula

    HDL implementation of various blocks in face recognition algorithm

  • M. Tech.

    Prashant Pathak

    HDL Implementation of LDPC Decoder for CCSDS standard

  • M. Tech.

    Nabajyoti Kumar Das (Co-supervisor)

    Image Feature Extraction using SIFT on FPGA

  • M. Tech.

    Swarupa Raut (Co-supervisor)

    Clock Distribution Planning for High Frequency

  • M. Tech.

    Deepak Kumar

    FPGA validation of different short codelength QC-LDPC decoder

  • M. Tech.

    Wilfred Kisku

    Acceleration of DL based algorithm (GOTURN) on Zynq SoC using Vivado HLS

  • M. Tech.

    Suman Pandit

    Design Automation using Eldo tool for efficient & faster design of clock cells

  • M. Tech.

    Priyanka Raju Ladda

    Validation and Verification of performance efficient graphics Architecture.

  • M. Tech.

    Divyesh Patel

    FPGA implementation of Software defined networking with OpenFlow

  • M. Tech.

    Vismay Kansara

    Design and implementation of Variable rate Quasi cycle LDPC code

  • M. Tech.

    Harshit Gupta

    FPGA implementation of Face tracking

  • M. Tech.

    Syam Sanal

    Implementation of Multi-threaded Image processing using ReconOS on Reconfigurable computing systems

  • M. Tech.

    Dharmesh Patel

    Design and implementation of Quasi Cycle LDPC Code

  • M. Tech.

    S Lakshmi Divya

    Implementation of Effective optimization strategies in Low power SoC physical design

  • M. Tech.

    Patel Swara J

    Register file design: challenges and optimization at sub0-micron nodes

  • M. Tech.

    Prasad Rasala

    DDR4 interface design verification for Xeon servers

  • M. Tech.

    Gaurav Paralikar

    Implementation of Microphone array for speech recognition enhancement

  • M. Tech.

    Jitenkumar Patel

    FPGA implementation of Memory based architecture for scale invariant feature transform

  • M. Tech.

    Swati Jaiyawala

    Implementation of Particle filter based object tracking on NoC Archiecture

  • M. Tech.

    Ashish Pandey

    Streaming Architecture for Image Processing

  • M. Tech.

    Keral Patel

    HDL implementation of LDPC decoder

  • M. Tech.

    Anudeep J

    GPU implementation of Earth Mover’s Distance

  • M. Tech.

    B Chandra Sekhar Naik

    FPGA implementation of Earth Mover’s distance

  • M. Tech.

    Deshmukh Gaurav Pradiprao

    SystemC Simulation model of the Scale Invariant Feature transform

  • M. Tech.

    Mukund Makwana

    FPGA implementationof LDPC codes

  • M. Tech.

    Divyesh Mori

    VHDL implementation of Hough transform

  • M. Tech.

    Rahul Mehta

    Multi-picoblaze implementation for Image Processing

  • M. Tech.

    Harshal Prajapati

    VHDL implementation of SIFT algorithm

  • M. Tech.

    Dhananjay Patel

    SIFT implementation on Many core Rigel Architecture

  • M. Tech.

    Sanjay Trivedi

    Design of a unified timing signal generator (UTSG) for pulsed radar

  • M. Tech.

    Himanshu Bhimani

    SIFT algorithm using GPU

  • M. Tech.

    SANTOSH PAVAN KUMAR D

    Design and verification of an Automated CRC Engine

  • M. Tech.

    Parthiv Bharti

    HDL implementation of Object Tracking using Kalman Filter

  • M. Tech.

    Amit Jain

    HDL Impelmentation of Object Tracking using Mean Shift Algorithm

  • M. Tech.

    Saurabh Vaidhya

    Reconfigurable FFT Processor

  • M. Tech.

    Love Jain

    VHDL Implementation of Sobel Edge Detector

  • M. Tech.

    Rathod Amit C

    Instruction Set Customization in Embedded Processor

  • M. Tech.

    GADDALA GOPALA KRISHNA

    A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY

  • M. Tech.

    Pinal K Patel

    Object tracking in online Video

  • M. Tech.

    B. Arun Kumar

    Finger Print recognition using Matlab