Academic Positions

  • Present 2007

    Assistant Professor

    S V National Instiute of Technology (SVNIT), Surat

  • 2007 2003

    Assistant Professor

    CSP Institute of Technolgy, Charotar University of Science & Technology (CHARUSAT), Changa

  • 2003 2001

    Temporary Lecturer

    Faculty of Technology & Engineering, M S University of Baroda, Vadodara

Education & Training

  • Ph. D. Pursuing

    Electrical Engineering

    Indian Institute of Technology(IIT) Bombay

  • M.E.2001

    Master of Engineering (Microprocessor Systems & Applications)

    M S University of Baroda, Vadodara

  • B.E.1999

    Bachelor of Engineering in Instrumentation & Control

    L D College of Engineering, Gujarat University, Ahmedabad

I always like to look on the optimistic side of life, but I am realistic enough to know that life is a complex matter.

Industry Interactions

  • 2017
    Amdocs Innovationa Lab - 2017
    image
    One team from SVNIT entered into Top 5 of Grand finale event of Amdocs Innovation Lab-2017.

Subjects

  • Embedded Systems
  • Advanced Processor Architecture
  • Real-time Systems
  • Digital Logic Design

Research Summary

Recent trends in deep-submicron very large-scale integration (VLSI) circuit technology have resulted in new requirements for algorithms in integrated circuit layout. Much of my work centers on new formulations that capture performance and density criteria in the physical layout phases of computer-aided design (CAD). Our results include near-optimal approximation algorithms for such computationally difficult problems as minimum-cost Steiner tree routing, low-skew clock networks, cost-radius tradeoffs, bounded-density trees, circuit probe testing, high-performing Elmore-based constructions, layout density control, and improved manufacturability.

Interests

  • Embedded Systems
  • High Performance Embedded Computing
  • Real-time Image Processing
  • Reconfigurable Computing

Laboratory Personel

Harshit Gupta

Postgraduate Student

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Rohit Singh

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Vismay Kansara

Postgraduate Student

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Shyam Sanal

Postgraduate Student

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Hemendra

Project Associate

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FPGA implementation of particle filter based object tracking in video

Sumeet Agrawal, Pinalkumar Engineer, Rajbabu Velmurugan, Sachin Patkar
Conference Papers International Symposium on Electronic System Design (ISED), 2012, Pages: 82-86

Abstract

There is a continuous requirement of enhancing the computation speed with minimum resources to improve performance of signal processing algorithm. This paper proposes an architecture and implementation of a modified color histogram based Particle filter for object tracking in video. This architecture implements weight calculation and histogram calculation in a highly parallel form. The proposed architecture occupies less resource saving by effective memory utilization. The performance of the algorithm is demonstrated using a single object scenario.

Modified architecture for real-time face detection using FPGA

Suraj Das, Atit Jariwala and Pinalkumar Engineer
Conference Papers 3rd Nirma University International Conference on Engineering (Nuicone-2012), Nirma University, Ahmedabad, Dec 6-8,2012, Pages. 1-5.

Abstract

In this paper, we introduce modified hardware architecture with key features of lessening the resource usage of the FPGA and elevating the face detection frame rate. The system is based on well-known Viola Jones Framework which consists of AdaBoost algorithm integrated with Haar features. We also enlist the modification in hardware design techniques to achieve more parallel processing and higher detection speed of the system. The system implemented on Xilinx Virtex-5 FPGA development board outputs a high face detection rate (91.3%) at 60 frame/second for a VGA (640 × 480) video source. The power consumption of the implementation is 2.1 W.

Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies

Vinay B. Y. Kumar, Pinalkumar Engineer , Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale and Sachin B. Patkar
Conference Papers Second International Workshop on FPGAs for Software Programmers (FSP 2015), September 1- 4, 2015

Abstract

The algorithm-to-hardware High-level synthesis (HLS) tools today are purported to produce hardware comparable in quality to handcrafted designs, particularly with user directive driven or domains specific HLS. However, HLS tools are not readily equipped for when an application/algorithm needs to scale. We present a (work-in-progress) semi-automated framework to map applications over a packet-switched network of modules (single FPGA) and then to seamlessly partition such a network over multiple FPGAs over quasi-serial links. We illustrate the framework through three application case studies: LDPC Decoding, Particle Filter based Object Tracking, and Matrix Vector Multiplication over GF(2). Starting with high-level representations of each case application, we first express them in an intermediate message passing formulation, a model of communicating processing elements. Once the processing elements are identified, these are either handcrafted or realized using HLS. The rest of the flow is automated where the processing elements are plugged on to a configurable network-on-chip (CONNECT) topology of choice, followed by partitioning the 'on-chip' links to work seamlessly across chips/FPGAs.

Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video

Pinalkumar Engineer , Rajbabu Velmurugan and Sachin B. Patkar
Conference Papers 28th International Conference on {VLSI} Design, {VLSID} 2015, Bangalore, India, January 3-7, 2015. pp. 35--40.

Abstract

Real-time particle filter based object tracking in videos on embedded platforms (FPGA) is challenging because of its resource usage and computational complexity. Furthermore, minor changes to the algorithm will need changes in the hardware. To address these issues, we propose a parametrizable FPGA framework for particle filter based object tracking algorithm. This parametrizable implementation can be used for various image sequences, object sizes and number of particles. By changing few parameters, this parametrization leads to appropriate changes in hardware resources resulting in efficient real-time operation of the algorithm. Experimental results show better tracking from the implementation and the proposed architecture can run particle filter algorithm for a color video sequence with 650 fps on average.

FPGA based stream processing of edge and skin detection algorithms

Suraj Das, Atit Jariwala and Pinalkumar Engineer
Conference Papers International Conference on Advanced Computing and Communication Technologies (ICACCT-2012)at Asia Pacific Institute of Information Technology SD India, Panipat (Haryana) on November 3,2012

Abstract

Mean-Shift Algorithm: Verilog HDL Approach

Rahul V. Shah, Amit Jain, Rutul B Bhatt, Pinalkumar Engineer and Ekata Mehul
Conference Papers Proceedings of the Third International Conference on Trends in Information, Telecommunication and Computing, 2013. Pages 181-194

Abstract

Combining Power of MATLAB with SystemVerilog for Image and Video Processing ASIC Verification

Dhaval Modi, Harsh Sitapara, Rahul Shah, Ekata Mehul, Pinalkumar Engineer
Conference Papers ADVANCES IN NETWORK SECURITY AND APPLICATIONS, Communications in Computer and Information Science series 2011, 196(1). Pages 181-193

Abstract

The ultimate Aim of ASIC verification is to obtain the highest possible level of confidence in the correctness of a design, attempt to find design errors and show that the design implements the specification. Complexity of ASIC is growing exponentially and the market is pressuring design cycle times to decrease. Traditional methods of verification have proven to be insufficient for Digital Image processing applications. We develop a new verification method based on SystemVerilog verification with MATLAB to accelerate verification. The co-simulation is accomplished using MATLAB and SystemVerilog coupled through the DPI. Here is used the Image Resize design verification as case study by using co-simulation method between SystemVerilog and MATLAB. Golden reference will be made using MATLAB In-built functions, while rest of the Verification Environment are in SystemVerilog. The goal is to find more bugs from the Design as compared to traditional method of Verification, reduce time to verify video processing ASIC, reduce debugging time, and reduce coding length

Enhancing verification capability using system Verilog and Matlab

Dhaval Modi, Harsh Sitapara, Rahul V Shah, Ekata Mehul, Pinalkumar Engineer
Conference Papers 2nd International conference on Signals, Systems and Automation (ICSSA-2011), January 2011

Abstract

Field Programmable Gate Array Based Control Signal Generator for Pulsed Radar

Sanjay Trivedi, B. S. Raman, Pinalkumar Engineer and Dr. Mihir Shah
Journal Paper International Journal of Embedded Systems and Applications (IJESA), 2(3): September 2012

Abstract

The objective of this paper is to present the architecture design and implementation of a software defined hardware module called Control Signal Generator (CSG) for pulsed RADAR (Radio Detection and Ranging) application. It is a digital, programmable, application-specific control timing signal generator for Disaster Management Synthetic Aperture Radar (DM-SAR)[1]. This module is a slave controller which receives command through asynchronous serial interface and generates programmable timings. Architecture evolved and the module is developed using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and successfully implemented on Xilinx Field Programmable Gate Array (FPGA) XCV600-6HQ240

Design of a Unified Timing Signal Generator (uTSG) for Pulsed Radar

Sanjay Trivedi, B. S. Raman, Pinalkumar Engineer and Dr. Mihir Shah
Journal Paper International Journal of Electronics and Communication Engineering & Technology (IJECET), 3(1): June 2012

Abstract

Integrating MATLAB with verification HDLs for functional verification of image and video processing ASIC

Dhaval Modi and Harsh Sitapara and Rahul V. Shah and Ekata Mehul and Pinalkumar Engineer
Journal Paper International Journal of Computer Science \& Emerging Technologies, 2(2):258--265, 2011

Abstract

The ultimate Aim of ASIC verification is to obtain the highest possible level of confidence in the correctness of a design, attempt to find design errors and show that the design implements the specification. Complexity of ASIC is growing exponentially and the market is pressuring design cycle times to decrease. Traditional methods of verification have proven to be insufficient for Digital Image processing applications. We develop a new verification method based on SystemVerilog verification with MATLAB to accelerate verification. The co-simulation is accomplished using MATLAB and SystemVerilog coupled through the DPI. I will be using the Image Resize design as case study by using co-simulation method between SystemVerilog and MATLAB. Golden reference will be made using MATLAB In-built functions, while rest of the Verification blocks are in SystemVerilog. The goal is to find more bugs from Image resizing Design as compared to traditional method of Verification, reduce time to verify video processing ASIC, reduce debugging time, and reduce coding length.

  • image

    Title of Project

    Very short description of the project.

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    Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui officia deserunt mollit anim id est laborum.

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Contact & Meet Me

I would be happy to talk to you if you need my assistance in your research or whether you need bussiness administration support for your company.

  •    office: +91-261-2201738
  •    lab: +91-261-2201575
  •    pje@eced.svnit.ac.in
  •    pinalengineer@gmail.com
  •    pinal_engineer
  •    #engineerpj
  •    www.linkedin.com/in/pinalengineer

At My Office

You can find me at my office located at Second floor of Electronics Engineering Department (New building)

I am at my office during office hours, but you may consider a call to fix an appointment.

At My Work

You can find me at my office located at Second floor of Electronics Engineering Department (New building)

I am at my office during office hours, but you may consider a call to fix an appointment.

At My Lab

You can find me at my lab (Embedded System Lab) located at First floor of Electronics Engineering Department (Old building)

I am at my office during office hours,, but you may consider a call to fix an appointment.